The present invention relates to a nonvolatile semiconductor memory having a stacked gate structure and, more particularly, to a nonvolatile semiconductor memory used in a NAND flash EEPROM.
A NAND flash EEPROM (Electrically Erasable and Programmable Read Only Memory) is well known as a nonvolatile semiconductor memory which can electrically change program data, and has a memory cell structure suitable for high integration of elements (large memory capacity).
FIG. 1 shows a memory cell array of the NAND flash EEPROM. FIG. 2 shows an example of the memory cell structure of the NAND flash EEPROM.
The memory cell array of the NAND flash EEPROM comprises a plurality of NAND cell units disposed in a matrix. Each NAND cell unit is constructed by NAND cells each consisting of a series circuit of a plurality of (16 in this case) memory cells, and two select gate transistors respectively connected to the end cells.
The memory cells and select gate transistors in each NAND cell unit are disposed in a p-well 12 in an n-well 11 formed on a p-semiconductor substrate 10, i.e., in a twin-well.
The memory cells in the NAND cell have a so-called stacked gate structure formed by stacking control gate electrodes CG0, . . . , CG15 on floating gate electrodes FG. Also, the select gate transistors have the same stacked gate structure as that of the memory cells, but only the lower layers serve as gate electrodes SGS and SGD in practice.
The control gate electrodes (word lines) CG0, CG1, . . . , CG15 respectively run in the row direction of the memory cell array, and are commonly connected to the memory cells in the same rows. Likewise, the select gate electrodes (select gate lines) SGS and SGD run in the row direction of the memory cell array, and are commonly connected to the select gate transistors in the NAND cell units in the same rows.
In each NAND cell unit, two neighboring transistors (memory cells and/or select gate transistor) share a single diffusion layer (source or drain) 13. Also, two neighboring NAND cell units in the column direction share a drain diffusion layer 13a or source diffusion layer 13b.
The select gate transistor on one end side (on the drain diffusion layer 13a side) of the NAND cell is connected to a bit line (data line) BLi, and the select gate transistor on the other end side (on the source diffusion layer 13b side) to a source line (reference potential line) SL. The source line SL is commonly connected to all the NAND cell units.
As one of data programming methods in the NAND flash EEPROM, a method called self boost programming is known.
When self boost programming is used, since all MOS transistors connected to a given bit line, MOS transistors that construct a column decoder, and the like can be driven by an external power supply potential Vcc or an internal power supply potential Vdd which is generated based on the external power supply potential Vcc and has a value lower than the external power supply potential Vcc, so-called low-voltage operation is allowed. That is, when self boost programming is used, the need for a booster circuit for supplying high potential to these MOS transistors can be obviated, and the total area of peripheral circuits around the memory cell array can be reduced, thus attaining a reduction of the chip area.
The procedures of the data program step based on self boost programming will be explained below.
The data erase step is done to set memory cells in an erase state ("1"-state). After that, data programming is executed in units of pages or bytes.
In the normal program step, in each NAND cell unit, programming is done in units of cells in the order from a memory cell farthest from a bit line (a memory cell on the source line side) toward memory cells on the bit line side. On the other hand, in random programming, programming is done for an arbitrary one of a series circuit of a plurality of memory cells connected between the bit and source lines.
As shown in FIG. 3, in self boost programming, a gate electrode (select gate line) SG2 of select gate transistors S21 and S22 on the source line side is set at 0V to set these select gate transistors S21 and S22 in a cutoff state.
Next, 0V (data "0") is applied to a bit line (selected bit line) BL1 to which a memory cell A (M21) that is to undergo "0"-programming ("0"-programming memory cell) is connected, and a plus potential (data "1") is applied to a bit line (unselected bit line) BL2 to which a memory cell B (M22) that is to undergo "1"-programming ("1"-programming memory cell), i.e., a program inhibition cell, is connected. This plus potential is set at a value equal to or higher than a potential applied to a gate electrode (select gate line) SG1 of select gate transistors S11 and S12 on the drain side.
At this time, the select gate transistor S11 on the drain side is turned on, and the potential (0V) on the bit line BL1 is transferred to the channel of the memory cell A (M21). Also, the select gate transistor S12 on the drain side is initially turned on, and an initial potential is transferred to the diffusion layer (source/drain) of the memory cell B (M22). After that, the select gate transistor S12 on the drain side is cut off.
Note that the plus potential applied to a bit line BL2 may be lower than that to be applied to the gate electrode (select gate line) SG1 of the select gate transistors S11 and S12 on the drain side. In this case, it is necessary to cut off the select gate transistor S12 on the drain side.
In this state, a selected word line (control gate line) WL2 is set at a program potential Vpp, and unselected word lines (control gate lines) WL1 and WL3 to WLN in the selected block are set at a passing potential Vpass (Vpp&gt;Vpass&gt;Vcc) that at least turns on memory cells.
For example, these potentials Vpp and Vpass are applied at the following timings.
The potential of the select gate line SG1 of the select gate transistors on the bit line side are set at a power supply potential Vcc. When the potentials of all the unselected word lines (control gate lines) are set at a passing potential Vpass, since memory cells M11 to MN1 and the select gate transistor S11 in the NAND cell unit connected to the bit line BL1 are turned on, the potential (0V) on the bit line BL1 are transferred to the channels of the memory cells M11 to MN1.
Also, to the channels of memory cells M12 to MN2 in the NAND cell unit connected to the bit line BL2 charges are transferred from the bit line BL2 via the select gate transistor S12. Hence, the channel potentials of the memory cells M12 to MN2 in the NAND cell unit connected to the bit line BL2 gradually rise, and reach an initial potential obtained by subtracting a threshold value Vth of the select gate transistor S12 from a bit line potential VBL2.
When the channel potentials have reached the initial potential, the select gate transistor S12 is cut off, and the channels of the memory cells M12 to MN2 float. At this time, 0V or a plus potential VSL which is high enough to cut off the select gate transistor S22 on the source side is applied to the source line. When the unselected word lines are set at Vpass, the potentials of the channel and the diffusion layer of the memory cell are boosted.
After that, a program potential pulse Vpp is applied to the selected word line WL2.
Hence, the channel potential of the "0"-programming memory cell A (M21) is set at 0V, and the potential of the word line (control gate line) WL2 is set at Vpp, thus executing a "0"-programming operation (an operation for injecting electrons into the floating gate electrode) for the memory cell A (M21).
On the other hand, the initial potential of the channel of the "1"-programming memory cell B (M22) is VBL2-Vth. On the other hand, since the channel of the memory cell B (M22) is floating, when the passing potential pulse Vpass is applied to the unselected word line WL1, WL3-WLN, the channel potential of the memory cell M12-MN2 rises due to capacitive coupling across the channel of the memory cell and the control gate line.
Hence, in the "1"-programming memory cell B (M22), since no high voltage is applied across the channel and control gate line, no electrons are injected into the floating gate electrode. That is, a "1"-programming operation (an operation for maintaining an erase state) is done for the memory cell B (M22).
In order to maintain the memory cell B (M22) erased, the channel potential of the memory cell B (M22) can be set to be sufficiently high, so that no high voltage is applied across the channel of the memory cell B (M22) and control gate line. That is, as for the memory cell B (M22), the channel potential value is set so that a variation of a threshold voltage due to the program pulse Vpp falls within an allowable range.
The channel potential of the selected memory cell B (M22) rises with increasing value of Vpass, and a variation of the threshold voltage of the memory cell B (M22) can be minimized.
Note that the above description is premised on a case wherein two-level data ("1", "0") is stored in a memory cell. Of course, self boost programming can be applied to a case wherein multi-level data (three-level or higher data) is stored in a memory cell. When multi-level data is stored in a memory cell, "1" of two-level data can be replaced by "0", and "0" of two-level data can be replaced by "1", "2", . . . , "N".
The operation sequence of self boost programming has been explained. In this programming, program errors occur upon data programming.
More specifically, as shown in FIG. 3, when "0"-programming (program with a positive threshold value) is done for the selected memory cell A (M21) connected between the word line WL2 and bit line BL2, program errors occur in the selected "1"-programming memory cell B, and an unselected memory cell C (M31).
Note that program errors are likely to occur in memory cells other than B and C in FIG. 3. More specifically, a problem that has taken place in the memory cell B also takes place in "1"-programming memory cells which are connected to bit lines other than the bit line BL2, and a problem that has taken place in the memory cell C takes place in all unselected memory cells in the NAND cell unit including the memory cell A.
Program error in the memory cell B (M22) will be explained below. The selected word line (control gate line) WL2 is set at the program potential Vpp. On the other hand, the initial potential of the channel of the memory cell B (M22) is VBL2-Vth. After that, when the program potential Vpp is applied to the selected word line WL2, and the passing potential Vpass is applied to the unselected word lines WL1, WL3, . . . , WLN, the channel potential of the memory cell B (M2) rises to a value higher than the initial potential due to capacitive coupling.
Therefore, in order to prevent any program error in the memory cell B (M22), Vpass must be set at a largest possible value to set a sufficiently high channel potential of the memory cell B (M22) and to relax the voltage across the channel of the memory cell B (M22) and the control gate line.
Program error in the memory cell C (M31) will be explained below. Upon data programming, the unselected word lines (control gate lines) WL1, WL3, . . . , WLN are set at Vpass (Vpp&gt;Vpass&gt;Vcc). On the other hand, the channel potential of the memory cell C (M31) is maintained at 0V.
Hence, in order to prevent any program error in the memory cell C (M31), Vpass must be set at a smallest possible value to relax the voltage across the channel of the memory cell C (M31) and the control gate line.
In this way, in the "0"-programming operation for the memory cell A (M21), a variation of the threshold voltage of the "1"-programming memory cell B (M22), and that of the unselected memory cell C (M31) must be minimized. However, when Vpass is set at a large value, a variation of the threshold voltage of the memory cell B (M22) becomes small, but that of the memory cell C (M31) becomes large. Conversely, when Vpass is set at a small value, a variation of the threshold voltage of the memory cell C (M31) becomes small, but that of the memory cell B (M22) becomes large.
For this reason, Vpass is set at an optimal value so that variations of the threshold voltages of the memory cells B and C fall within an allowable range.
Note that the program error problem and the problem upon determining an optimal value of Vpp in self boost programming will be described in detail later.
FIGS. 4A and 4B show a capacitance formed in the memory cell.
The capacitance formed in the memory cell includes a capacitance C1 formed between the channel and control gate electrode CG, and a junction capacitance C2 formed between the channel (n.sup.+ -diffusion layer) and the p-well 12. The capacitance C1 consists of a capacitance formed between the channel and floating gate electrode (charge accumulation layer) FG, and a capacitance formed between the floating gate electrode FG and control gate electrode (CG).
For example, when a potential Vcg is applied to the control gate electrode CG, a channel potential Vch of the memory cell becomes {C1/(C1+C2)}.times.Vcg, as shown in FIG. 4B. That is, the potential Vcg of the control gate electrode CG and the channel potential Vch of the memory cell satisfy Vch=.alpha..times.Vcg. This constant (C1/(C1+C2)) is called a boost ratio (or boost ratio) of the channel.
Upon data programming, a potential Vcg of a control gate electrode CG of a selected sell in a selected block is set at a high program potential Vpp, and potentials Vcg of control gate electrodes CG of unselected cells in the selected block are set at Vpass (Vcc&lt;Vpass&lt;Vpp).
In a NAND cell unit including the selected cell which is to undergo "1"-programming (to maintain it erased), channel potentials Vch of individual memory cells rise on the basis of potentials Vcg of the control gate electrodes CG and the boost ratio .alpha.. Finally, the channel potentials Vch of the respective memory cells in this NAND cell unit are finally uniformed and rise up to a predetermined value.
Normally, the values Vpass and Vpp are gradually stepped up like an initial potential, step potential, and final potential, and the pulse widths of Vpass and Vpp are optimized. Such step-up programming is effective for narrowing down the threshold voltage distribution range after "0"-programming of a selected cell which is to undergo "0"-programming (to raise the threshold value from an erase state), and to prevent "0"-programing (program errors) of a selected "1"-programming cell, and of unselected cells.
In the NAND flash EEPROM, the memory cell array is normally segmented into a plurality of blocks. Data erase is done in units of blocks (block erase) or is simultaneously done for all the blocks (chip erase). In block erase, data in memory cells within a predetermined block can be erased, and data in memory cells in a plurality of arbitrary blocks can be erased. Also, in chip erase, data in memory cells in all the blocks are simultaneously erased.
Chip erase is don e by setting all control gate lines (word lines) in the memory cell array at 0V, setting the potentials of all select gate line s at Vpp (e.g. 18V), and applying a high erase potential (e.g., 20V) to a p-well. At this time, electrons in floating gate electrodes are released into the p-well due to the tunnel effect, and the threshold values of memory cells change in the negative direction.
Block erase is done by setting all control gate lines (word lines) in a selected block at 0V, setting all control gate lines and all select gate lines in unselected blocks at Vpp (e.g., 18V), setting the bit and source lines BL and SL in a floating state, and applying a high erase potential (e.g., 20V) to the p-well. At this time, in memory cells in the selected block, electrons in floating gate electrodes are released into the p-well due to the tunnel effect, and the threshold values of the memory cells change in the negative direction.
Note that all the select gate lines in chip erase and the control gate lines and all the select gate lines in the unselected blocks may be set at a predetermined potential which is higher than 0V and is equal to or lower than the erase high potential (e.g., 20V) in place of Vpp, or may float.
After data erase, verify read is done to verify if threshold values of all the memory cells to be erased fall within a predetermined threshold value range within which an erase state is determined. Based on data read out from the memory cells by verify read, erase OK or NG is determined, and if erase NG (insufficient) is determined, data erase is redone.
When the threshold voltage of a memory cell which stores data "1" is negative, and that of a memory cell which stores data "0" is positive, data read is done by precharging the potential of the bit line BL to a precharge potential in advance, then applying a read potential (e.g., 3.5V) to the select gate lines in the selected blocks and unselected control gate lines so as to keep select gate transistors and unselected memory cells ON, and applying 0V to the selected control gate line.
At this time, since memory cells for one page connected to the selected control gate line are turned on or off in accordance with their threshold voltages, memory cell data ("0" or "1") can be read out by detecting a change in potential of the bit line BL by a sense amplifier. Since the select gate lines in unselected blocks are set at 0V, select gate transistors in the unselected blocks are kept OFF.
The device structure of the conventional NAND flash EEPROM will be explained below.
FIG. 5 is a plan view showing an example of the device structure of the conventional NAND flash EEPROM. FIG. 6 is a sectional view taken along a line VI--VI in FIG. 5, and FIG. 7 is a sectional view taken along a line VII--VII in FIG. 5.
The memory cell array of the NAND flash EEPROM comprises a plurality of NAND Cell units disposed in a matrix. Each NAND cell unit is constructed by NAND cells each consisting of a series circuit of a plurality of (16 in this case) memory cells, and two select gate transistors respectively connected to the end cells.
The memory cells and select gate transistors in each NAND cell unit are disposed in a p-well 12 in an n-well 11 formed on a p-semiconductor substrate 10, i.e., in a twin-well.
Each memory cell in the NAND cell has, on a gate insulating film (tunnel oxide film) 4, a so-called stacked gate structure formed by stacking a control gate electrode 7 on a floating gate electrode 5 via an interpoly insulating film (ONO film) 6. Also, each select gate transistor has the same stacked gate structure as that of the memory cell, but only the lower layer serves as a gate electrode in practice.
Control gate electrodes (word lines) 7 run in the row direction of the memory cell array, and are commonly connected to memory cells in the same rows. Likewise, select gate electrodes (select gate lines) run in the row direction of the memory cell array, and are commonly connected to select gate transistors in NAND memory cell units in the same rows.
In each NAND cell unit, two neighboring transistors (memory cells and/or select gate transistor) share a single diffusion layer (source or drain) 1a. Also, two NAND cell units neighboring in the column direction share a drain diffusion layer 1b or source diffusion layer 1c.
The select gate transistor on one end side (on the drain side) of the NAND cells is connected to a bit line (data line) 9 via a bit line contact portion 14 formed in an insulating interlayer 8, and the select gate transistor on the other end side (on the source side) to a source line (reference potential line) 15 via a source line contact portion 16 formed in the insulating interlayer 8. The source line 15 is commonly connected to, e.g., all the NAND cell units.
In the NAND flash EEPROM shown in FIGS. 5 to 7, an isolation region 3a that surrounds an element region 3 is a field oxide film formed by LOCOS. Instead, as shown in, e.g., FIGS. 8 and 9, the isolation region 3a may be formed by a silicon oxide film with an STI (Shallow Trench Isolation) structure.
In the conventional NAND flash EEPROM using self boost programming, the following problems are posed in association with the memory cell structure, process, operation (e.g., the channel potential of a "1"-programming cell upon programming), and the like.
FIG. 10 shows the timing waveforms of potentials to be applied to the memory cells upon self boost programming.
A potential VBL1 of a bit line BL1 to which a "0"-programming memory cell is connected is set at 0V, and a potential VBL2 of a bit line BL2 to which a "1"-programming memory cell is connected is set at a power supply potential Vcc (e.g., 3.3V). Also, a potential vsg2 of a select gate line SG2 on the source side is set at 0V, and a potential Vsg1 of a select gate line SG1 on the bit line side is set at the power supply potential Vcc. At this time, two select gate transistors in a NAND cell unit which includes the "1"-programming memory cell are turned off, and the channels and diffusion layers of the memory cells in this NAND cell unit electrically float.
After that, when a potential VWL2 of a selected word line WL2 is set at a program potential Vpp, and potential VWL1 and VWL3 to VWLN of unselected word lines WL1 and WL3 to WLN are set at a passing potential Vpass (Vcc&lt;Vpass&lt;Vpp), a potential Vch of the channel (in the floating state) of the "1"-programming memory cell is boosted to a predetermined value.
Note that the channel potential of the "1"-programming memory cell and potentials to be applied to the memory cells satisfy: EQU Vch=Vsg-Vsgth (Vchinit)+Cr1(Vpass-Vpassth-Vchinit)+Cr2(Vpp-Vchinit)-(Tpw/16Cch).times.I (1)
where Vsg corresponds to the potential Vsg1 of the select gate line SG1 on the bit line side (drain side), and is set at, e.g., the power supply potential Vcc. Vchinit is the initial potential transferred from the bit line to the channel of each memory cell, Vsgth(Vchinit) is the threshold value of the select gate transistor on the bit line side when the channel potential is Vchinit, Cr1 is the boost ratio of the channel of each memory cell to which Vpass is applied, and Cr2 is the boost ratio of the channel of each memory cell to which a program pulse Vpp is applied.
Also, Vpassth is the potential required for the memory cell applied with Vpass to turn it on when the channel potential is Vch, Tpw is the pulse width of the program pulse Vpp, Cins is the capacitance per memory cell, Cch is the sum of the capacitance of a depletion layer lying under the channel, and the junction capacitance between the diffusion layer and p-well, and I is the total of currents that flow from the channel to the wells and bit line.
More specifically, by applying the program potential Vpp to the selected word line, and applying the passing potential Vpass (Vcc&lt;Vpass&lt;Vpp) to unselected word lines, the potential of the channel (floating state) of a "1"-programming memory cell is boosted to Vch. For this reason, in the "1"-programming memory cell, hardly any electrons are injected into the floating gate electrode, and an erase state is maintained, thus preventing program errors ("0"-programming).
However, the channel potential of the "1"-programming cell does not sufficiently rise, and program errors occur.
For example, variations of the concentration profile of an impurity (e.g., boron) in the p-well in which the select gate transistors and memory cells are formed, the concentration profile of an impurity doped into the channels of the select gate transistors and memory cells, and the concentration profile of an impurity in the diffusion layers (source/drain) of the select gate transistors and memory cells often lower the initial potential Vchinit transferred from the bit line to the channels. Also, an increase in capacitance formed in the depletion layer under the channels lower the boost efficiencies (Cr1, Cr2) of the channels. In this case, the channel potential of a "1"-programming memory cell does not sufficiently rise upon programming, the threshold value of that memory cell rises, and as a result, a program error ("0"-programming) occurs in that memory cell.
FIG. 11 shows the relationship between the variations of the threshold values of memory cells which do not undergo "0"-programming and the value of the passing potential Vpass to be applied to unselected word lines in the program operation.
Assume that cells A, B, and C indicate those shown in FIG. 3, and data in these memory cell are set in a "1"-state (erase state). Also, cell A is a "0"-programming cell, cell B is a "1"-programming cell, and cell C is an unselected cell (non-programming cell).
When Vpass is set at a low value, the channel potential of selected "1"-programming cell B does not sufficiently rise upon "0"-programming of selected cell A, and electrons are injected into the floating gate electrode of selected cell B. For this reason, as indicated by the dotted curve in FIG. 11, the threshold value of selected "1"-programming cell B gradually rises from an initial value Vth1, and exceeds the boundary between "1"- and "0"-states indicated by the one-dashed chain line. As a consequence, a program error ("0"-programming) takes place in selected "1"-programming cell B.
On the other hand, when Vpass is set at a sufficiently high value, the channel potential of selected "1"-programing cell B sufficiently rises upon "0"-programming of selected cell A. For this reason, as indicated by the solid curve in FIG. 11, the threshold value of selected "1"-programming cell B maintains Vth1 (erase state), and any program error ("0"-programming) can be prevented (i.e., "1"-programming is done).
As for unselected cell C, 0V is transferred from the bit line to its channel and its channel potential is fixed at 0V, as in selected cell A.
Therefore, when the Vpass value is too high, upon "0"-programming of selected cell A a high voltage is applied across the control gate electrode and channel of unselected cell C, and electrons are injected into the floating gate electrode of unselected cell C. For this reason, as indicated by the broken curve in FIG. 11, the threshold value of unselected cell C gradually rises from the initial value Vth1, and exceeds the boundary between "1"- and "0"-states indicated by the one-dashed chain line. As a consequence, a program error ("0"-programming) takes place in unselected cell C.
When the Vpass value is set to be sufficiently low upon "0"-programming of selected cell A, the voltage applied across the control gate electrode and channel of unselected cell C is relaxed. As a result, as indicated by the broken curve in FIG. 11, the threshold value of unselected cell C maintains Vth1 (erase state), and any program error ("0"-programming) is prevented.
In this way, a sufficiently high Vpass value must be set to prevent any program error in selected "1"-programming cell, while a sufficiently low Vpass value must be set to prevent any program error in unselected cell C.
Therefore, in order to prevent any program errors in all cells which do not undergo "0"-programming, the range of the passing potential Vpass must be selected so that the threshold values (solid and broken curves) after the program operation are always set below the boundary (one-dashed chain curve) between the "1"- and "0"-states, and the Vpass value must be determined from that range.
However, variations of the threshold values of the memory cells upon data programming are also influenced by variations of the gate width, gate length, and wing width (the width of the floating gate electrode on the isolation region) of each memory cell, the thickness of a tunnel oxide film, the thickness of an interpoly insulating film (an insulating film on the floating gate electrode), and the like during the wafer process.
That is, even when the Vpass value is set at an optimal value, program errors often occur in cells which do not undergo "0"-programming upon data programming due to variations of the dimensions and the like of the memory cells in the wafer process.
Upon programming, the passing potential Vpass and program potential Vpp are applied to memory cells in a selected block in the memory cell array. For this reason, when the dimensions of the memory cells vary in the wafer process, variations of the threshold values upon programming become larger with increasing number of memory cells (the number of bits) per block.
Hence, when memory cells are miniaturized to increase the number of memory cells per NAND cell unit or those connected to a single word line, the aforementioned problem of program errors occurs. That is, the program error problem upon programming disturbs miniaturization of memory cells.
As memory cells shrink further in feature size, the breakdown voltage in the source-to-drain path of the select gate transistor poses a problem. In order to set the breakdown voltage at a sufficiently large value, the amount of impurity doped into the channels of the memory cells and select gate transistors must be increased.
When the trench depth of the isolation region of the STI structure becomes smaller upon higher integration of memory cells, punch through, field inversion (inversion of the conductivity type of a semiconductor layer immediately under the isolation region), and the like occur, and a leakage current is generated between two memory cells which oppose each other to sandwich the isolation region therebetween (or between neighboring bit lines). To prevent such leakage current, the impurity concentration of a trench bottom portion of the isolation region of the STI structure must be increased or the concentration of the well must be increased.
However, when the impurity concentration of the trench bottom portion of the isolation region of the STI structure or the well concentration is increased, the boost ratio of the channel of each memory cell decreases. That is, miniaturization of memory cells results in a decrease in boost ratio of their channels, and the channel potential Vch of a selected "1"-programming cell cannot be sufficiently boosted.
When the trench width (the width in the direction in which the word line runs, i.e., in the row direction) of the isolation region of the STI structure becomes smaller as a result of higher integration of memory cells, the capacitance formed between the channels or diffusion layers of two memory cells neighboring in the row direction increases. Such increase in capacitance also results in a decrease in boost ratio of the channel. For this reason, upon programming, the channel potential Vch of a selected "1"-programming cell cannot be sufficiently boosted.
In this manner, variations of dimensions resulting from the structure and manufacturing process of memory cells and select gate transistors largely influence program errors in cells which do not undergo "0"-programming. For this reason, in order to achieve miniaturization and high integration of memory cells, the structure, manufacturing process, and operation of memory cells and select gate transistors must be improved to solve the program error problem resulting from variations of dimensions of memory cells and select gate transistors.
As one technique for achieving miniaturization of memory cells while preventing program errors in terms of the device structure, the present inventor has already proposed a NAND flash EEPROM having a channel boost capacitance (CBC) gate structure.
FIG. 12 is a plan view of a NAND flash EEPROM having the CBC gate structure. FIG. 13 is a sectional view taken along a line XIII--XIII in FIG. 12.
The structure of memory cells and select gate transistors is substantially the same as that of the conventional NAND flash EEPROM, except that a channel boost capacitance gate 17 is formed on each control gate electrode CG via a thin silicon oxide film. The channel boost capacitance gate 17 is electrically connected to the diffusion layer of each memory cell.
Since this structure can increase the coupling capacitance between the control gate electrode CG and channel, the channel potential of a "1"-programming cell which does not undergo "0"-programming can be sufficiently boosted upon self boost programming, thus preventing program errors.
Also, the CBC gate structure can lower the Vpass value compared to any non-CBC gate structure. That is, a variation of the threshold value of unselected cell C in a NAND cell unit including selected "0"-programming cell A can be reduced, and any program errors for unselected cell C can be prevented. Furthermore, even when Vpass is decreased, since the channel potential of "1"-programming memory cell B can be sufficiently boosted, program errors for this memory cell B can also be prevented.
Moreover, as the program potential Vpp can be set at a low value, a booster circuit for generating Vpp can be reduced in scale, thus contributing to a reduction of the chip size.
However, in the CBC gate structure, the channel boost capacitance gate must be connected to the diffusion layer of each memory cell, resulting in a complicated manufacturing process and high cost.
As the conventional programming schemes of the NAND flash EEPROM, so-called local self boost programming is known in addition to the aforementioned self boost programming.
FIG. 14 shows an example of potentials applied to memory cells in the program operation based on local self boost programming.
In local self boost (to be abbreviated as LSB hereinafter) programming, a power supply potential Vcc is applied to a select gate line SG1 on the bit line side, and 0V is applied to a select gate line SG2 on the source line side. Zero V is transferred from a bit line BL1 to the channel of a selected cell M21 in a NAND cell unit including a "0"-programming memory cell. Also, an initial potential Vcc-Vth is transferred from a bit line BL2 to the channel of a selected cell M22 in a NAND cell unit including a "1"-programming memory cell.
The potentials of a selected word line WL2, and word lines WL1 and WL3 on both sides of the line WL2 are kept at 0V, and those of other unselected word lines WL4 to WLN are raised to Vpass. At this time, the channel potential of the selected cell M22 in the NAND cell unit including the "1"-programming memory cell rises, and at least the selected cell M22 and unselected cells M12 and M32 on both sides of the cell M22 are cut off due to the back bias effect of the channels.
After that, when a program potential Vpp is applied to the selected word line WL2, a high voltage is applied across the control gate electrode (Vpp) and channel (0V) in the selected cell M21, thus making "0"-programming. On the other hand, in the selected cell M22 which does not undergo "0"-programming, the channel potential rises due to capacitive coupling between the control gate electrode and channel, thus avoiding "0"-programming.
Assuming that the program potential Vpp is 18V, and the boost ratio of the channel of the memory cell M22 is 0.5, the channel potential of the memory cell M22 is boosted up to about 8 to 9V. This value is high enough to prevent any program errors in the memory cell M22.
The aforementioned LSB programming is promising when it is applied to a multi-level memory that stores three-level or higher data in a single memory cell, but suffers the following problems in the current stage.
In LSB programming, when the program potential Vpp is applied to the selected word line WL2, the memory cells M12 and M32 on both sides of the memory cell M22 which is connected to the selected word line WL2 and does not undergo "0"-programming must be cut off. However, since these memory cells M12 and M32 have arbitrary threshold values, they may be in an erase state. For this reason, in order to cut off the memory cells M12 and M32, Vpass must be set at a sufficiently large value or the memory cells M12 and M32 must have sufficiently small erase threshold values (negative values with smaller absolute values).
However, if Vpass value is set at a large value, since high voltages are applied across the control gate electrodes and channels of unselected cells M41 to MN1 whose channel potentials are set at 0V, and program errors are highly likely to occur, it is difficult to set Vpass at a sufficiently large value. Upon erase operation, the threshold value distribution range of each erased memory cell may be narrowed down, and a sufficiently small erase threshold value may be set. However, since the erase time becomes very long in this case, such control cannot be adopted in terms of memory operations.
In LSB programming as well, each channel preferably has a largest possible boost ratio. For this reason, LSB programming may be used in the aforementioned NAND flash EEPROM with the CBC gate structure. However, in this case, problems of the complicated manufacturing process, an increase in layout area of memory cells, and the like due to addition of the CBC gates still remain unsolved.
As described above, a future subject of the NAND flash EEPROM is to develop the device structure, process, or operation method that can simultaneously meet the following requirements in self boost programming or LSB programming:
(1) to improve the boost ratio of each channel without increasing the number of manufacturing steps or complicating the manufacturing process; PA1 (2) to assure a sufficiently high boost ratio even when memory cells are miniaturized; PA1 (3) to prevent a decrease in boost ratio of each channel and avoid program errors even when the amount of impurity doped into the channels of memory cells increases due to miniaturization; PA1 (4) to obviate the need for controlling the threshold value distribution of memory cell after erase in LSB programming, and to obviate the need for any special circuit compared to the conventional NAND flash EEPROM; and PA1 (5) to avoid program errors even when the upper limit of a threshold value increases in a multi-level memory constructed by memory cells having a plurality of threshold values.
Of these objectives, the objective of preventing program errors can be achieved by sufficiently raising the channel potential of the selected "1"-programming cell connected to the selected word line to which Vpp is applied. When a high channel potential is set, program errors can be sufficiently prevented even when the threshold value of the unselected memory is highest in a multi-level memory constructed by memory cells having a plurality of threshold values.
However, the channel potential cannot be sufficiently increased for the following reason especially in a NAND flash EEPROM manufactured according to the design rule of 0.20 .mu.m or less.
The select gate transistor of the conventional NAND flash EEPROM mainly has two roles. One role is to disconnect NAND cell units in an unselected block from the bit line in the read mode, and the other role is to disconnect a NAND cell unit which does not include any "0"-programming memory cell from the bit line and to set the channels of the memory cells in that NAND cell unit in a floating state.
The ion implantation conditions for the channels and diffusion layers (source/drain) of the select gate transistors, well concentration, and the like are set to satisfy these roles. However, in recent years, as the device geometries shrink further, it is demanded to perform ion implantation for the channels and diffusion layers of the select gate transistors in the same process as that for the channels and diffusion layers of the memory cells.
When these ion implantation processes are to be done in a single step, the ion implantation conditions are set to make each select gate transistor fulfill the above-mentioned two roles. However, in this case, in each memory cell, a large capacitance is formed between the channel or diffusion layer (source/drain) and well, the channel boost ratio lowers, and a large channel potential cannot be obtained.
In self boost programming and LSB programming, it is important that the breakdown voltage of the drain be large in association with the cutoff characteristics, as well as the boost performance of the channel of each memory cell.
Upon boosting the channel of each memory cell, the drain or source potential of the select gate transistor rises to 5 to 8V. At this time, if a leakage current is generated in the source-to-drain path of the select gate transistor, and the cutoff characteristics become insufficient, the channel and diffusion layer (source/drain) of each memory cell cannot be sufficiently boosted, resulting in program errors.
Therefore, the leakage current must be prevented from being generated, and the cutoff characteristics of the select gate transistor must be sufficiently improved. In general, in order to prevent the leakage current of the select gate transistor and to sufficiently improve its cutoff characteristics, it is effective to increase the threshold value of the select gate transistor and to suppress a depletion layer from forming from the drain junction surface to the channel by setting a high impurity concentration of the channel.
In particular, when miniaturization progresses and the gate length becomes small, the amount of impurity doped into the channel must be increased. For this reason, the boost ratio of the channel further decreases, and program errors readily occur. Also, as miniaturization evolves, variations of the program characteristics become large due to, e.g., the short channel effect or the like and, as a result, program errors increase.
When ion implantation for the channel is made to satisfy the cutoff characteristics of each select gate transistor, the initial potential to be transferred from the bit or source line to the channel of each memory cell via the select gate transistor decreases, and the channel potential after boost drops.
In this case, the program characteristics of each memory cell excessively improve, and a change in threshold value of a memory cell to which Vpass is applied becomes large.
Such problems commonly occur when the NAND flash EEPROM adopts self boost programming or LSB programming.
In the future, the voltages to be supplied to the chip are projected to drop further. In such case, if the power supply voltage Vcc drops due to some cause, the initial potential Vchinit to be transferred to the channel of a memory cell which does not undergo "0"-programming lowers, and program errors readily occur.
As miniaturization progresses, due to the short channel effect of select gate transistors and memory cells, the threshold values and program/erase characteristics of these transistors vary, and the program/erase time becomes longer, thus producing leakage currents in the select gate transistors.